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71M6513/71M6513H
A Maxim Integrated Products Brand
3 -Phase      Energy Meter IC
DATA SHEET
AUGUST 2011
System Timing Summary
Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV =0 (six mux states) and FIR_LEN = 0 (2 CK32 cycles). Since FIR filter conversions require
two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1 + 3 *
states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
ADC MUX Frame
ADC TIMING
CK32
MUX_SYNC
150
MUX_DIV Conversions ( MUX_DIV =6 is shown)
Settle
MUX STATE
S
0
1
2
3
4
5
S
ADC EXECUTION
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
CE TIMING
0
300
600
900
1200
1500
1800
CE_EXECUTION
CK COUNT = CE_CYCLES + floor(CE_CYCLES + 2) / 5)
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM and SSI TIMING
RTM
SSI
LAST SSI TRANSFER
MAX CK COUNT
140
BEGIN SSI TRANSFER
NOTES:
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
Page: 50 of 104
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